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for further information contact your local stmicroelectronics sales office. september 2014 docid025765 rev 3 1/16 STA8088CWG gps/galileo/glonass/qzss receiver data brief features ? stmicroelectronics ? 3 rd generation positioning receiver with 32 tracking channels and 2 fast acquisition channels compatible with gps, galileo and glonass systems ? embedded rf front-end with separate gps/galieo/qzss and glonass if outputs ? embedded low noise amplifier ? -162 dbm indoor sensitivity (tracking mode) ? fast ttff <1 s in hot start and 35s in cold start ? high performance arm946 mcu (up to 208 mhz) ? 256 kbyte embedded sram ? real time clock (rtc) circuit ? 32-bit watch-dog timer ? 2 uarts ? 1 i 2 c master/slave interface ? 1 external sqi flash interface ? usb2.0 dual-role full speed (12 mhz) with integrated physical layer transceiver ? 2 controller area network (can) ? 2 channels adc (10 bits) ? 3 embedded 1.8 v voltage regulators ? i/o level selectable 1.8 v or 3.3 v ? operating condition: ?v dd12 : 1.2 v 10% ?v dd18/rf18 : 1.8 v 5% ?v lpvr 1.62 v to 3.6 v ?v ddio : 1.8 v 5%; 3.3 v 10% ? package: ? wl-csp77 (4 x4 x0.6 mm) ? ambient temperature range: -40/+85c description STA8088CWG is a single die standalone positioning receiver ic working on multiple constellations (gps/galileo/glonass/qzss). the minimum bom and small wl-csp package (16 mm 2 ) make STA8088CWG the ideal solution for low-cost and small footprint products such hand-held computers, cameras, data loggers, and sports accessories. the device is offered with a complete gnss firmware which performs all gnss operations including tracking, acquisition, navigation and data output. wl-csp77 gapgcft01085 www.st.com
contents STA8088CWG 2/16 docid025765 rev 3 contents 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.2 wl-csp77 ball out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.3 power supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.4 main function pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.5 test/emulated dedicated pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.6 rf front-end pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.7 port 0 pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.8 port 1 pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.1 ecopack ? packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.2 wl_csp77 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
docid025765 rev 3 3/16 STA8088CWG list of tables 3 list of tables table 1. wl-csp77 ball out (top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 2. power supply pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 3. main function pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 4. test/emulated dedicated pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 5. rf front-end pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 6. port 0 pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 7. port 1 pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 8. wl_csp77 4 x 4 x 0.6 mm package dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 9. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
list of figures STA8088CWG 4/16 docid025765 rev 3 list of figures figure 1. STA8088CWG system block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2. wl_csp77 4 x 4 x 0.6 mm package dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 3. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
docid025765 rev 3 5/16 STA8088CWG overview 15 1 overview STA8088CWG is a highly integrated system-on-chip device designed for positioning systems applications. the low power consumption and minimum bom make STA8088CWG the ideal solution for low-cost and battery-operated portable products such handheld, computers, cameras, data loggers and sports accessories, as well as automotive application. it combines a high performance arm946 microprocessor with embedded enhanced peripherals and i/o capabilities with st next generation triple-constellation positioning engine. the rf front-end and base band processor are able to support gps/galileo and glonass navigation systems. the device is offered with a complete firmware which performs all positioning operations including tracking, acquisition, navigation and data output. it also provides clock generation via pll, backup logic with real time clock and it supports usb2.0 standard at full speed, (12 mbps) with on-chip phy. STA8088CWG is software compatible with the arm processor family. the device is power supplied with 1.8v and uses three on-chip voltage regulators to internally supply the rf front-end, core logic and the backup logic. in order to reduce the power consumption the chip can be directly powered with 1.2 v bypassing the embedded voltage regulators which will be put in power down mode. i/o lines are compatible with 1.8 v and 3.3 v. the chip, using stmicroelectronics cmosrf technology, is housed in a wl-csp77 (4 x 4 x 0.6 mm) package.
pin description STA8088CWG 6/16 docid025765 rev 3 2 pin description 2.1 block diagram figure 1. STA8088CWG system block diagram bk_domain sqi if usb if vic rom 16kb ahb dcreg osci32 thsens saradc ad10sa1m_18 osci32 osci32_lj_1v8 pwr, rst & clk ctrl iso cell i2c ssp uart2 rx - tx regmap apb bridge2 uart1 rx - tx adc mtu gpio eft wd apb arm 946 i-cache 16kb d-cache 8kb high speed i - tcm 64kb 64khigh speed d ? tcm 8 apb bridge1 sys ctrl rtc apb ram 8kb g3 base band glonass if galgps if 2 fast acq channel 32 trk channels mux acq rams apb bridge dc_ln_1v8to1v2 hpreg lpreg bkreg clock_gen ckx2 pll pg_650x frc_dpll riosc47 test controller ios jtag g3rf ip 1.8v 1.2v dcreg spi if osci 26mhz rf section lna section adc galgps adc glonass i/d switchable tcm 8x16kb gapgcft00543 can1 can0
docid025765 rev 3 7/16 STA8088CWG pin description 15 2.2 wl-csp77 ball out 2.3 power supply pins table 1. wl-csp77 ball out (top view) 12345678 9 a vdd_ ior1 vdd_ior1 vdd_ ior3 vdd12_ mvr2 usb_dm tdo tdi vdd_ ior5 gnd b sqi_ sio0_si sqi_sio1_ so gpio53 usb_dp can0tx can0rx i2c_sd i2c_sclk tms c sqi_cen sqi_sck sqi_sio3 gnd gnd gnd tck trstn vdd18_ mvr2 dsqi_sio2 timer_ ocmpb timer_ ocmpa gnd gnd gnd gnd tp_if_n tp_if_p e uart2_ rx gpio14 timer_ icapa uart2_tx gnd gnd gnd vrf12_ lna vrf12_ rfadc f gpio0 adc_in5 gnd vdd12_ lpvr gnd gnd gnd_ lna lna_in gnd_lna g adc_in1 vdd12_ mvr3 rtc_xti vdd12_ mvr1 xtal_ out gnd vrf18_ rfvr lna_out ? h vdd18_ mvr1 rtc_xto wakeup stdbyn xtal_in vrf12_ mix_if vrf12_ rfa vrf12out_ rfvr ? j vdd18_ mvr1 vdd_ lpvr rstn stdby_ out vrf12_ rfvco ?rfa_in ? vrf12_ rfa table 2. power supply pins symbol i/o functions wl-csp77 vdd18_mvr[1,2] pwr digital supply voltage for main voltage regulator (1.8 v) h1, j1, c9 vdd12_mvr[1,2,3] pwr digital supply voltage for core circuitry (1.2 v). when using the mvr, this pin shall not be driven by an external voltage supply, but a capacitance shall be connected between these pins and gnd to guarantee on-chip voltage stability. g4, a4, g2 vdd_lpvr pwr digital supply voltage for low power voltage regulator (1.62 - 3.6 v) j2 vdd12_lpvr pwr digital supply voltage for backup logic (1.2 v). when using the lpvr, this pin shall not be driven by an external voltage supply, but a capacitance shall be connected between these pins and gnd to guarantee on-chip voltage stability. f4 vdd_ior1 pwr digital supply voltage for i/o ring 1 (1.8 or 3.3 v) a1, a2 vdd_ior3 pwr digital supply voltage for i/o ring 3 (1.8 v); this pin can be connected to ground if the related i/o ring is not used a3 vdd_ior5 pwr digital supply voltage for i/o ring 5 (3.3 v); this pin can be connected to ground if the related i/o ring is not used a8
pin description STA8088CWG 8/16 docid025765 rev 3 2.4 main function pins vrf18_rfvr pwr analog supply voltage for rf voltage regulator (1.8 v) g7 vrf12out_rfvr pwr rf voltage regulator 1.2 v output h8 vrf12_lna pwr analog supply voltage for lna (1.2 v) e8 vrf12_rfa pwr analog supply voltage for rfa (1.2 v) h8, j9 vrf12_mix_if pwr analog supply voltage for mixer and if (1.2 v) h6 vrf12_rfvco pwr analog supply voltage for vco (1.2 v) j5 vrf12_rfadc pwr analog supply voltage for rf adc (1.2 v) e9 gnd_lna gnd analog supply ground for lna f7, f9 gnd gnd analog and digital supply ground a9, c4, c5, c6, d4, d5, d6, d7, e5, e6, e7, f3, f5, f6, g6 table 2. power supply pins (continued) symbol i/o functions wl-csp77 table 3. main function pins symbol i/o voltage i/o functions wl_csp77 stdbyn 1.2v i when low, the chip is forced in standby mode - all pins in high impedance except the ones powered by backup supply h4 stdby_out 1.2v o when low, indicates the chips is in standby mode j4 rstn (1) 1.2v i reset input with schmitt-trigger characteristics and noise filter. j3 wakeup (2) 1.2v i wakeup from standby mode h3 rtc_xti 1.5v (max) i input of the 32khz oscillator amplifier circuit and input of the internal real time clock circuit. g3 rtc_xto 1.5v (max) o output of the oscillator amplifier circuit. h2 adc_in[1,5] 1.4v ? 0 typ range i adc analog input [1,5] g1, f2 usb_dp/ uart1_tx vdd_ior5 usb/o usb d+ signal/ uart1 tx data b4 usb_dm/ uart1_rx vdd_ior5 usb/i usb d- signal/ uart1 rx data a5 can0tx vdd_ior5 o can0 - transmit data output b5 can0rx vdd_ior5 i can0 - receive data input b6 1. when rstn is de-asserted, pin wakeup must be low. 2. the wakeup pulse must be longer than 500 s.
docid025765 rev 3 9/16 STA8088CWG pin description 15 2.5 test/emulated dedicated pins 2.6 rf front-end pins 2.7 port 0 pins port 0 consists of a 32-bit bidirectional i/o port (only 7-bit are used in STA8088CWG). it can be either used as general purpose input or output port, or configured according to the associated alternate functions. table 4. test/emulated dedicated pins symbol i/o voltage i/o functions wl_csp77 tdo vdd_ior5 o jtag test data out a6 tdi vdd_ior5 i jtag test data in a7 tck vdd_ior5 i jtag test clock c7 tms vdd_ior5 i jtag test mode select b9 trstn (1) vdd_ior5 i jtag test circuit reset c8 tp_if_p vrf12_if o diff. test point for if ? positive d9 tp_if_n vrf12_if o diff. test point for if ? negative d8 1. if jtag interface is not used, pin trstn must be asserted low. table 5. rf front-end pins symbol i/o voltage i/o functions wl_csp77 lna_in vrf12_lna i low noise amplifier input f8 lna_out vrf12_lna o low noise amplifier output g8 rfa_in vrf12_rfa i rf amplifier input j7 xtal_in vrf12_rfvco i input side of crystal oscillator or tcxo input h5 xtal_out vrf12_rfvco o output side of crystal oscillator g5 table 6. port 0 pins symbol i/o voltage i/o mode functions wl_csp77 p0.0 vdd_ior1 i/o default gpio.0: general purpose i/o f1 i a pps_in: pulse per second input o b pps_out: pulse per second output p0.8 vdd_ior5 o default can1tx: can1 transmit data output b7 i/o a gpio.8: general purpose i/o i/o b i2c_sd: i2c serial data
pin description STA8088CWG 10/16 docid025765 rev 3 2.8 port 1 pins port 1 consists of a 32-bit bidirectional i/o port (only9-bit are used in STA8088CWG). it can be either used as general purpose input or output port, or configured according to the associated alternate functions. p0.9 vdd_ior5 i default can1rx: can1 receive data input b8 i/o a gpio.9: general purpose i/o o b i2c_sclk: i2c clock p0.14 vdd_ior5 i/o a gpio.14: general purpose i/o e2 p0.15 vdd_ior5 i/o a gpio.15: general purpose i/o e3 o b timer_icapa: extended function timer - input capture a p0.16 vdd_ior5 i/o a gpio.16: general purpose i/o d3 ob timer_ocmpa: extended function timer - output compare a p0.18 vdd_ior5 i/o a gpio.18: general purpose i/o d2 ob timer_ocmpb: extended function timer - output compare b table 6. port 0 pins (continued) symbol i/o voltage i/o mode functions wl_csp77 table 7. port 1 pins symbol i/o voltage i/o mode functions wl_csp77 p1.0 vdd_ior1 odefault sqi_cen: sqi flash chip enable i/o. ring 1 power selection c1 i/o a gpio32: general purpose i/o i/o b signggps: ggps 3-bit coding output (sign) p1.1 vdd_ior1 o default sqi_clk: sqi flash clock c2 i/o a gpio33: general purpose i/o i/o b clock_ggps: ggps clock out p1.2 vdd_ior1 i/o default sqi_sio0/si: sqi flash data i/o 0 / ser. i b1 i/o a gpio34: general purpose i/o i/o b signgns: gns 3-bit coding output (sign) p1.3 vdd_ior1 i/o default sqi_sio1/so: sqi flash data i/o 1 / ser. o b2 i/o a gpio35: general purpose i/o i/o b clock_gns: gns clock out
docid025765 rev 3 11/16 STA8088CWG pin description 15 p1.4 vdd_ior1 i default uart2_rx: uart 2 rx data e1 i/o a gpio36: general purpose i/o p1.5 vdd_ior1 i/o default uart2_tx / boot_0: uart 2 tx data / arm boot 0 e4 i/o a gpio37: general purpose i/o p1.6 vdd_ior1 i/o default sqi_sio2: sqi flash data i/o 2 d1 i/o a gpio38: general purpose i/o p1.7 vdd_ior1 i/o default sqi_sio3/boot_1: sqi flash data i/o 3/armboot 1 c3 i/o a gpio39: general purpose i/o p1.21 vdd_ior3 i/o a gpio53: general purpose i/o b3 table 7. port 1 pins (continued) symbol i/o voltage i/o mode functions wl_csp77
package and packing information STA8088CWG 12/16 docid025765 rev 3 3 package and packing information 3.1 ecopack ? packages in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. 3.2 wl_csp77 package information table 8. wl_csp77 4 x 4 x 0.6 mm package dimensions symbol min. typ. max a 0.54 0.57 0.6 a1 0.175 0.19 0.205 a2 0.355 0.38 0.405 b 0.245 0.27 0.295 x3.985 y4.065 number of bumps: 77
docid025765 rev 3 13/16 STA8088CWG package and packing information 15 figure 2. wl_csp77 4 x 4 x 0.6 mm package dimension ("1($'5
ordering information STA8088CWG 14/16 docid025765 rev 3 4 ordering information figure 3. ordering information scheme packing gnss tr = tape and reel = tray g = gps/glonass/galileo/qzss = gps/qzss sal housed in wl_csp sta8088cw tr g example code: family identifier
docid025765 rev 3 15/16 STA8088CWG revision history 15 5 revision history table 9. document revision history date revision changes 10-jan-2014 1 initial release. 12-feb-2014 2 updated features list table 3: main function pins : ? can0tx, can0tx: removed note table 6: port 0 pins : ? p0.8, p0.9: removed note figure 3: ordering information scheme 24-sep-2014 3 table 3: main function pins : ? rstn, wakeup: added note table 4: test/emulated dedicated pins : ? trstn: added note
STA8088CWG 16/16 docid025765 rev 3 important notice ? please read carefully stmicroelectronics nv and its subsidiaries (?st?) reserve the right to make changes, corrections, enhancements, modifications, and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant in formation on st products before placing orders. st products are sold pursuant to st?s terms and conditions of sale in place at the time of o rder acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and st assumes no liability for application assistance or the design of purchasers? products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information set forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2014 stmicroelectronics ? all rights reserved

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